Several trends exist today in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated that are small and portable, thereby relying on a small battery as its supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices that are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device that has a fair amount of memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device that retains its contents while a signal is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (“EEPROM”) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory that utilizes a ferroelectric material, such as strontium bismuth tantalate (SBT) or lead zirconate titanate (PZT), as the capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture affect the read and write access times of a FeRAM. Table 1 illustrates the differences between different memory types.
TABLE 1FeRAMPropertySRAMFlashDRAM(Demo)Voltage>0.5 VRead >0.5 V>1 V3.3 VWrite (12 V) (±6 V)Special TransistorsNOYESYESNO(High Voltage)(Low Leakage)Write Time<10 ns100 ms<30 ns60 nsWrite Endurance>1015<1015>1015>1013Read Time (single/multi-bit)<10 ns<30 ns<30 ns/<2 ns60 nsRead Endurance>1015>1015>1015>1013Added Mask for embedded0~6–8~6–8~3Cell Size (F~metal pitch/2)~80 F2~8 F2~8 F2~18 F2ArchitectureNDRONDRODRODRONon volatileNOYESNOYESStorageIQQP
Ferroelectric memory devices, and other types of semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric capacitors (FeCaps) adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FeCap to one of a pair of complimentary bit lines, with the other bit line being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of plate lines and word lines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage where data memory cells include capacitors constructed with ferroelectric dielectric material that may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. Although the polarization of each individual dipole is relatively small, the net polarization of several domains, each comprising a number of aligned dipoles, can be large enough for detection using, for example, standard sense amplifier designs. The gross effect of polarization is a nonzero charge per unit area of the ferroelectric capacitor that does not disappear over time.
A plot 10 of the characteristic hysteresis loop for a conventional ferroelectric capacitor is shown in FIG. 1A, and displays the total charge on the ferroelectric capacitor as a function of the applied voltage. Plot 10 illustrates the charge “Q” (Y-axis), and the voltage “V” (X-axis). Remnant charge (Qr), saturation charge (Qs), and coercive voltage (Vc) are three important parameters that characterize the loop. When the voltage across the capacitor is 0V, the capacitor assumes one of the two stable states: “0” 15 or “1” 20. The total charge stored on the capacitor is Qr for a “0” 15 or −Qr for a “1” 20. A “0” can be switched to a “1” by applying a negative voltage pulse across the capacitor. By doing so, the total charge on the capacitor is reduced by 2Qr, a change of charge that can be sensed by the sense amplifier (amp). Similarly, a “1” can be switched back to a “0” by applying a positive voltage pulse across the capacitor, hence restoring the capacitor charge to +Qr.
Characteristic curve segment 25 represents the charge path of a FeCap from a “1” state 20, thru Vcc as charge is applied, and then thru curve segment 30 to the other stable “0” state 15 as the voltage is relaxed to the FeCap. FIG. 1B is the schematic symbol 50 of the FeCap of FIG. 1A with capacitance CFE, while the “+” and “−” signs beside the FeCap symbol represent the applied voltage polarity.
Ferroelectric thin films, such as those made of PZT are promising materials for FeRAM use, however, problems still remain concerning its integration within the silicon process. One of the biggest problems that PZT suffers in the integration is the disappearance of polarization hysteresis characteristics and an increase of leakage current during passivation in an atmosphere containing hydrogen. It has been documented that hydrogen attaches to the PZT film degrading the switched polarization characteristics and increasing the leakage current of the PZT layer.
As current trends continue, the need for increased levels of device integration and process scaling has also increased. One consequence of process technology scaling is the need for higher densities of low resistivity circuit elements as scaling continues downward. Additionally, with the increasing number of scaled down memory cells required on a chip, FeRAM cells need to be manufactured to a high degree of uniformity for the associated read/write circuitry.
Accordingly, there is a need for high density FeRAM memory circuits having low resistivity circuit elements manufactured with processes that insure a high level of uniformity between memory cells, while retaining the switched polarization and low leakage characteristics of the PZT layer.